moduleSHIF(DIN，CLK，RST，DOUT);inputCLK，DIN，RST;outputDOUT;reg[]SHFT;always@(posedgeCLKorposedgeRST)if(RST)SHFT<=’B;elsebeginSHFT>);SHFT[]<=DIN;endassignDOUT=SHFT[];endmodule该程序实现的功能是：